The present invention relates to the field of electronic design automation for electronic circuits, and more specifically to techniques of validating simulation results for electronic circuits, especially when simulated using an approximation or reduction method.
The age of information and electronic commerce has been made possible by the development of electronic circuits and their miniaturization through integrated circuit technology. Integrated circuits are sometimes referred to as “chips.” Some type of integrated circuits include digital signal processors (DSPs), amplifiers, dynamic random access memories (DRAMs), static random access memories (SRAMs), erasable programmable read only memories (EPROMs), electrically erasable programmable read only memories (EEPROMs), Flash memories, microprocessors, application specific integrated circuits (ASICs), and programmable logic.
Integrated circuits have been widely adopted and are used in many products in the areas of computers and other programmed machines, consumer electronics, telecommunications and networking equipment, wireless network and communications, industrial automation, and medical instruments, just to name a few. Electronic circuits and integrated circuits are the foundation of the Internet and other on-line technologies including the World Wide Web (WWW).
There is a continuing demand for electronic products that are easier to use, more accessible to greater numbers of users, provide more features, and generally address the needs of consumers and customers. Integrated circuit technology continues to advance rapidly. With new advances in technology, more of these needs are addressed. Furthermore, new advances may also bring about fundamental changes in technology that profoundly impact and greatly enhance the products of the future.
To meet the challenges of building more complex and higher performance integrated circuits, software tools are used. These tools are in an area commonly referred to as computer aided design (CAD), computer aided engineering (CAE), or electronic design automation (EDA). There is a constant need to improve these electronic automatic tools in order to address the desire for higher integration and greater complexity, and better performance in integrated circuits.
Large modern day integrated circuits have millions of devices including gates and transistors, and are very complex. As process technology improves, more and more devices may be fabricated on a single integrated circuit, so integrated circuits will continue to become even larger and more complex with time. In the past, many parasitic effects may not have been considered because they were less significant or insignificant compared to other factors.
As lithography and miniaturization techniques advance, on-chip devices and line widths become smaller, frequencies increase. As a consequence, many more impedances such as parasitic resistances, inductances, and capacitances and parasitic effects need to be considered. If these parasitics and effects are not taken into account, poor simulation results will result, and possible the electronic circuits will not work as expected after the circuit is fabricated. As more and more parasitic and other effects are accounted for, the circuit networks to be simulated become larger and much more complex. Further, electronic systems at the board level are becoming more complex, thus increasing circuit network simulation size and complexity. As network size and complexity increases, simulating the network takes significantly more computing resources and computation time.
Simulating large, complex networks to obtain an exact solution is time consuming. Such simulations can take may take many hours, days, or even weeks. Circuit simulation is an order n-cubed problem. So, as the number of nodes increases, the time increases significantly. Therefore, to reduce the simulation time, approximation or reduction methods are used to simulate the networks. Some of these techniques are known as fast-Spice or fast-MOS techniques.
These techniques estimate the simulation results, and do not provide an exact solution. In an approximation method approach, certain circuit information is thrown away or not considered. The approach may be iterative. By reducing the amount of information to consider, the estimated simulation results may be obtained much faster than trying to find the exact solution. For example, an exact solution for a circuit with 600,000 nodes may be obtained in 38 hours with Spice, but using an approximation method, the results may be obtained in 10 minutes.
There are shortcomings to the approximation or reduction approaches to circuit simulation because they trade off accuracy for performance. Accuracy is reduced because the estimated simulation results are estimates rather than an exact solution. Further, even though the developer of the circuit simulation estimation software markets the estimated results as being accurate, the user will not know the degree of accuracy of the simulation results. For some circuit networks, an approach may provide results which are within 1 percent of the exact solution, which may be acceptable depending on the circuitry. But for some circuit networks, the same approach may give results that are more than 5 percent off, which may be unacceptable.
Therefore, there is a need for techniques of validating the results from circuit simulation estimation software.